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Poly depletion is also a major device design issue, particularly for sub-0.25-jim dualgate (n+ gate for n-MOS and p+ gate for p-MOS) CMOS, which is prevalently used in the high-performance CMOS technologies because both the n-MOS and p-MOS can be maintained in the surface channel operation mode which is good for shortchannel effect and thus device scaling. However, the dual-gate CMOS also requires 62 63 some tradeoffs, most notably boron penetration (for p-MOS) and poly depletion. , Boron penetration refers to the boron in the p+-doped poly diffusing through the gate oxide, which is a poor diffusion barrier for boron, and affects the VTp, transistor performance, as well as reliability. The schemes for alleviating the boron penetration are discussed in more detail in the following section. The poly depletion problem for the dual-gate CMOS is due to the fact that when gate bias is applied to turn the transistor on, the electrical field in the gate oxide will not only invert the substrate but also penetrate into the gate electrode and deplete the gate poly. Therefore, poly depletion is dependent on the dopant concentration in the poly (and close to the poly/ oxide interface) and the gate oxide thickness. Poly depletion is obviously an issue for high-performance CMOS because it reduces the drive current of the transistor.64 Although for a high fan-out circuit the performance impact may not be very large because both drive current and gate capacitance are reduced by the same factor, lower drive current is certainly a critical issue for driving large interconnect capacitance (see Eq. 10.6) because the signal delay time in the interconnect network 63 has become the performance bottle neck for high-performance VLSI circuits. For a dual-gate CMOS, the relationship between poly depletion and poly concentration can be expressed as: make barcodes excel 2003 Barcode Add in for Word and Excel Free Download
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